Z80 Datasheet, PDF (131/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Initiate Read Sequence (A7)
This command initiates the read-sequence pointer command, allowing the
next CPU read instruction to the DMA access to the first (low-order) read
register designated as readable by the read mask. When started, the read
sequence specified by the read mask must be completed before, for
example, giving another INITIATE READ SEQUENCE or a READ
STATUS BYTE command.
Registers do not need to be read immediately after writing the INITIATE
READ SEQUENCE command. Other commands (except INITIATE READ
SEQUENCE and READ STATUS BYTE) can be written and can go through
bus-request/bus release cycles before executing the first read and subse-
quent reads.
Force ReadY (B3)
This command, in Burst or Continuous mode, forces an internal Ready
condition to take the place of an external active Ready signal. It is used for
memory-to-memory transfers and memory searches where no Ready line is
necessary. Ready active High/Low (bit 3 of WR5) need not be considered
when this command is used. The FORCE READY condition is unforced by
the following commands and conditions:
• RESET command
• LOAD command
• RESET AND DISABLE INTERRUPTS command
• End-of-block termination
• Byte-match termination
• Bus release by DMA
Because bus release by the DMA unforces the Ready condition, this
command allows the DMA to transfer only one byte in the byte mode.
UM008101-0601
Direct Memory Access