Z80 Datasheet, PDF (223/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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D7 D6 D5 D4 D3 D2 D1 D0
11 0 1 01 10
Selects A5, A3, and A0 to be Monitored
If a sensor puts a High level on lines A5, A3, or A0, an interrupt request is
generated. The mask word may select any combination of inputs or
outputs to cause an interrupt. For example, if the mask word above is:
D7 D6 D5 D4 D3 D2 D1 D0
010 1 01 10
then an interrupt request would also occur if bit A7 (Special Test) of the
output register was set.
Assume that the following port assignments are to be used:
E0H = Port A Data
E1H = Port B Data
E2H = Port A Control
E3H = Port B Control
All port numbers are in hexadecimal notation. This particular assignment of
port numbers is convenient because A0 of the address bus can be used as
the Port B/A Select and A1 of the address bus can be used as the Control/
Data Select. The Chip Enable is the decode of CPU address bits A7 through
A2 (111000).
Note: When only a few peripheral devices are being used, a Chip Enable
decode may not be required because a higher order address bit may be
used directly.
UM008101-0601
Parallel Input/Output