Z80 Datasheet, PDF (85/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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system buses, it indicates a DMA-controlled write to a memory or
I/O port address.
RESET
Reset (input, active Low) is available in the CMOS PLCC version only. A
Low in this signal resets the DMA.
System
Data
Bus
BUS
Control
System
Control
BUS
D0
A0
D1
A1
D2
A2
D3
A3
D4
A4
D5
A5
D6
D7
A6
A7
A8
A9
BUSREQ
A10
BAI
A11
BAO
Z80 DMA
A12
A13
A14
M1
A15
IORQ
MREQ
RD
WR
RESET
RDY
C5/WAIT
INT/PULSE
IEI
IEO
System
Address
Bus
DMA
Control
Interrupt
Control
+5V GND CLK
C-MOS DMA
PLCC Package Only
Figure 25. Pin Functions (CMOS PLCC Package Only)
UM008101-0601
Direct Memory Access