Z80 Datasheet, PDF (297/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
277
Table 14. Reset Commands
CRC Reset
Code 1
0
0
1
1
CRC Reset
Code 0
0
1
0
1
Result
Null Code (no affect)
Reset Receive CRC Checker
Reset Transmit CRC Generator
Reset Tx Underrun/End of Message latch
The Reset Transmit CRC Generator command normally initializes the CRC
generator to 0s. If the SDLC mode is selected, this command initializes the
CRC generator to 1s. The Receive CRC checker is also initialized to 1s for
the SDLC mode.
Write Register 1
WR1 (Figure 115) contains the control bits for the various interrupt and
Wait/Ready modes.
Table 15. Write Register 1
D7
D6
Wait/Ready
Enable
Wait or Ready
Function
D3
D2
Receive Interrupt Status Affects
Mode 0
Vector
D5
D4
Wait/Ready on Receive Interrupt
Receive Transmit Mode 1
D1
D0
Transmit Interrupt External Interrupts
Enable
Enable
External/Status Interrupt Enable (D0)
The External/Status Interrupt Enable allows interrupts to occur as a result of
transitions on the DCD, CTS, or SYNC inputs, as a result of a Break/Abort
UM008101-0601
Serial Input/Output