Z80 Datasheet, PDF (121/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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D7 D6 D5 D4 D3 D2 D1 D0
1
0 1 Base Register Byte
Byte = 0 0
Continuous = 0 1
Burst = 1 0
Do Not Program = 1 1
Port B Starting Address
(Low Byte)
Port B Starting Address
(High Byte)
0
Interrupt on RDY = 1
Status Affects Vector = 1
Interrupt Control Byte
1 = Interrupted on Match
1 = Interrupted at End-of-Block
1 = Pulse Generated
Pulse Control Byte
Interrupt Vector
Vector is automatically
Modified as shown only if
Status Affects Vector bit is set
0 0 = Interrupt on RDY
0 0 = Interrupt on Match
0 0 = Interrupt on End-of-Block
0 0 = Interrupt on Match and End-of-Block
Figure 44. Write Register 4 Group
Write Register 5 Group
Bits 7, 6, 2, 1, and 0, illustrated in Figure 45, specify the base register byte
for this one register group. The byte is used to specify these characteristics:
UM008101-0601
Direct Memory Access