Z80 Datasheet, PDF (93/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Address and Byte Counting
Addresses for either port may be fixed at their programmed starting
address, or they may be incremented or decremented from the programmed
starting address by the address counters. The block length programmed into
the DMA is compared with the byte counter, which starts at zero and incre-
ments at the completion of each byte operation (Figure 20).
The DMA uses a high-speed buffering or pipelining scheme for reading
data. When transferring data and stopping on an end-of-block, the effect of
this pipelining is that one more transfer is completed than is programmed
into the block-length register; the only exception to this rule occurs in
simultaneous transfers that use two-cycle variable timing, in which case
two extra bytes are transferred if the Ready line remains active.
Table 11 describes the contents of the counters in the various classes and
the modes of transfer involving stopping or interrupting at an end-of-block
(interrupts imply prior stopping).
Search and transfer/search operations that are programmed to stop on byte
match function somewhat differently, as described in Table 12. Matches are
discovered only after the next byte is read. In all classes of transfer/search
operations, the matched byte is transferred. In simultaneous transfer/search
operations, however, an additional byte is usually also transferred. The only
exception to this occurs in Burst and Continuous modes when the Ready
line goes inactive while the byte match is being located. During simulta-
neous transfer/searches in Burst or Continuous mode, these searches are
typically continuous processes performed in memory using a Force Ready
condition or a Ready line that will not go inactive. However, when this
exception is encountered, the CPU can be programmed to research two
bytes when such a match occurs.
UM008101-0601
Direct Memory Access