Z80 Datasheet, PDF (221/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Interrupts are then enabled by the rising edge of the first M1 after the inter-
rupt mode word is set unless that first M1 defines an interrupt acknowledge
cycle. If a mask follows the interrupt mode word, interrupts are enabled by
the rising edge of the first M1 following the setting of the mask.
Data can now be transferred between the peripheral and the CPU. The
timing for this transfer is as described in “Timing” on page 192.
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Figure 15. Example of I/O Interface
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Parallel Input/Output