Z80 Datasheet, PDF (126/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

< %27 2GTKRJGTCNU
7UGT /CPWCN

the routine is being executed. Near the end of the routine, the CPU writes
an ENABLE INTERRUPTS command to the DIVA, which enables it to
generate a new interrupt.
This command is less extensive than the RESET AND DISABLE INTER-
RUPTS command because it does not reset the Interrupt Pending (IP) and
Interrupt Under Service (IUS) latches.
D7 D6 D5 D4 D3 D2 D1 D0
1
1 1 Base Register Byte
Hex Command Name
1 0 0 0 0 = C3 = Reset
1 0 0 0 1 = C7 = Reset Port A Timing
1 0 0 1 0 = C8 = Reset Port B Timing
1 0 0 1 1 = CF = Load
1 0 1 0 0 = D3 = Continue
0 1 0 1 1 = AF = Disable Interrupts
0 1 0 1 0 = AB = Enable Interrupts
0 1 0 0 0 = A3 = Reset and Disable Interrupts
0 1 1 0 1 = B7 = Enable after RETI
0 1 1 1 1 = BF = Read Status Byte
0 0 0 1 0 = 8B = Reinitialize Status Byte
0 1 0 0 1 = A7 = Initialize Read Sequence
0 1 1 0 0 = B3 = Force Ready
0 0 0 0 1 = 87 = Enable DMA
0 0 0 0 0 = 83 = Disable DMA
0 1 1 1 0 = BB = Read Mask Follows
0
Read Mask (1=Enable)
Status Byte
Byte Counter (Low Byte)
Byte Counter (High Byte)
Port A Address (Low Byte)
Port A Address (High Byte)
Port B Address (Low Byte)
Port B Address (High Byte)
Figure 46. Write Register 6 Group
UM008101-0601
Direct Memory Access