Z80 Datasheet, PDF (116/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Write Register 2 Group
Bits 7, 2, 1, and 0, depicted in Figure 42, specify the base register byte for
this group. The group is used only when Port B is used, for example, do not
program it for a search-only, simultaneous transfer, or simultaneous
transfer/search with Port A as the source. Its syntax is the same as WR1.
D7 D6 D5 D4 D3 D2 D1 D0
0
0 0 0 Base Register Byte
0 = Port B is Memory
0 = Port B is I/O
0 0 = Port B Address Decrements
0 1 = Port B Address Increments
1
1
0
1
= Port B Address Fixed
Port B Variable
Timing Byte
WR Ends 1/2 Cycle Early = 0
RD Ends 1/2 Cycle Early = 0
MREQ Ends 1/2 Cycle Early = 0
0 0 = Cycle Length = 4
0 1 = Cycle Length = 3
1 0 = Cycle Length = 2
1 1 = Do Not Use
0 = IORQ Ends 1/2 Cycle Early
Figure 42. Write Register 2 Group
Write Register 3 Group
Bits 7, 1, and 0, depicted in Figure 43, specify the base register byte for this
group. The group is used primarily to specify the stop-on-match condition
as well as the specific match byte for a search operation. It can perform fast,
one-byte enabling of both bus requests and interrupts. A description of its
functions follows.
UM008101-0601
Direct Memory Access