Z80 Datasheet, PDF (309/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
289
D7 D6 D5 D4 D3 D2 D1 D0
Tx CRC Enable
RTS
SDLC/CRC-16
Tx Enable
Send Break
0
0 8-Bit SYNC Character
0
1 16-Bit SYNC Character
1
0 SDLC Mode (0111 1110 Flag)
1
1 External SYNC Mode
DTR
Figure 119. Write Register 5
Transmit Bits/Characters 0 and 1 (D5 and D6)
Together, D6 and D5 control the number of bits in each byte transferred to
the transmit buffer.
Table 27. Transmit Bits
D6 Transmit Bits/
Character 1
0
0
1
1
D5 Transmit Bits/
Character 0
0
1
0
1
Bits/Character
Five or less
7
6
8
Bits to be sent must be right justified, least-significant bits first. The Five-
Or-Less mode allows transmission of one to five bits per character;
however, the CPU should format the data character as depicted in the
following table.
UM008101-0601
Serial Input/Output