Z80 Datasheet, PDF (219/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Highest Priority Channel
Port 1A
Port 2A
Port 1B
Port 2B
+
HI _IEI
IEO ^HI IEI
IEO ^HI IEI
IEO ^HI IEI
IEO ^HI
1. Priority interrupt daisy chain before any interrupt occurs.
+
HI _IEI
IEO ^HI IEI
Under Service
IEO ^HI IEI
IEO
LO _IEI
2. Port 2A requests an interrupt and is Acknowledged.
+
HI _IEI
Under Service
Service Suspended
IEO ^HI IEI
IEO ^LO IEI
IEO ^LO IEI
3. Port 1B1 interrupts, suspends servicing of Port 2A.
+
HI _IEI
Service Complete Service Resumed
IEO ^HI IEI
IEO ^HI IEI
IEO ^LO IEI
4. Port 1B service routine complete, ‘RETI’ issued, Port 2A service resumed.
+
HI _IEI
IEO ^HI IEI
Service Complete
IEO ^HI IEI
IEO ^HI IEI
5. Second ‘RETI’ instruction issued on completion of Port 2A service routine.
LO
IEO
LO
IEO
LO
IEO
HI
IEO
Figure 13. Daisy-Chain Interrupt Servicing
APPLICATIONS
Extending The Interrupt Daisy-chain
Without external logic, a maximum of four Z80 PIO devices may be daisy-
chained into a priority interrupt structure. This limitation allows the inter-
rupt enable status (IEO) to ripple through the entire daisy-chain between
the beginning of M1 and the beginning of IORQ during an interrupt
acknowledge cycle. The interrupt enable status cannot change during M1,
therefore, the vector address returned to the CPU is assured to be from the
highest priority device that requested an interrupt.
UM008101-0601
Parallel Input/Output