Z80 Datasheet, PDF (55/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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DMA Characteristics
All DMACs are programmable because the CPU must at least write a
block length (byte count) and starting memory address to a DMAC before
they can begin managing a data transfer. The starting address is incre-
mented or decremented as the transfer proceeds, and the byte counter is
incremented from zero up to the specified block length.
In addition to being programmable, DMACs vary in characteristics and
capabilities.
Ports and Channels
Every data transfer has a source and a destination. For example, in
memory-to-I/O transfers, memory is the source and I/O is the destination
port. The means of controlling and tracking the data exchange between the
two ports is called a channel. A channel includes the hardware for address
and byte counting, bus control, and coordination of the entire transfer
process.
The location for each source and destination for a channel is specified
either by the DMA address-generation mechanism or by hardwiring. The
Z80 DMA generates addresses for both memory and I/O ports during each
byte transfer.
Some DMACs have multiple channels, which means that they can keep
track of multiple interleaved transfers, and that one DMA can be hardwired
to multiple I/O devices. However, because any DMA can execute only one
read and/or write cycle at a time, multiple channels do not mean higher
throughput than single channels in a given speed. The Z80 DMA is a
single-channel device that can generate addresses to perform memory-to-
memory data transfers. I/O port addresses on the address bus.
The Z80 DMA can also perform internal byte searches. When the Z80 DMA
loads bytes to an internal DMAC register during transfers, the result is that,
when a byte is loaded, it can be compared with a maskable control byte.
UM008101-0601
Direct Memory Access