Z80 Datasheet, PDF (107/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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are allowed in which the higher priority peripheral suspends the execution
of the lower priority peripheral’s service routine.
Bus-requesting daisy-chains do not have this preemption or nesting
ability. Instead, any peripheral that is able to get the bus keeps it until task
completion.
Z80
INT
CPU
INT
+5V
IEI
IEO
Highest Priority
Interrupting Device
Figure 37. Interrupt Daisy-Chain
INT
IEI
IEO
To
Lower
Priority
Interrupting
Device
Polling for Service Requests
When the CPU cannot detect interrupts directly, it polls an external gate as
shown in Figure 38.
Polling is accomplished in the following way:
• Enable the DMA’s interrupt structure with a control byte
• Poll a status bit to see when an interrupt request occurs
tristate enable line, normally at tristate,
for example, connected to a chip select decoder.
INT
DMA
Pending
Polling
CPU
UM008101-0601
Direct Memory Access