Z80 Datasheet, PDF (38/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Bit
Number
4
3
Field
CLK/TRG Edge
Section
Time Trigger*
2
Time Constant
1
Reset
0
Control or Vector
*TIMER mode only
R/W
R/W
R/W
R/W
R/W
R/W
Value Description
1 Rising Edge
0 Falling Edge
1 CLK/TRG Pulse Starts Timer
0 Automatic trigger when time constant is loaded
1 Time Constant Follows
0 No Time Constant Follows
1 Software Reset
0 Continue Operation
1 Control
0 Vector
Bit 7 = 1. Each channel is enabled to generate an interrupt request sequence
when the down-counter reaches a zero-count condition. To set the interrupt
bit to 1 in any of the four Channel Control registers an interrupt vector is
written to the CTC before operation begins. Channel interrupts may be
programmed in either Counter or Timer mode. If an updated channel
control word is written to a channel in operation, with bit 7 set, the interrupt
enable selection is not retroactive to a preceding zero-count condition.
Bit 7 = 0. Channel interrupts disabled.
Bit 6 = 1. Counter mode selected. The down-counter is decremented by
each triggering edge of the External clock (CLK/TRG) input. The prescaler
is not used.
Bit 6 = 0. Timer mode selected. The prescaler is clocked by the System
clock Φ, and the output of the prescaler in turn clocks the down-counter.
The output of the down-counter (the channel’s ZC/TO output) is a uniform
pulse train of period given by the product as shown below
8_-
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UM008101-0601
Counter/Timer Channels