Z80 Datasheet, PDF (109/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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chapter. It is not possible for the DMA to program itself by directing
transfers of control bytes from memory to its own internal registers.
When DMA interrupt vectors are used in a Z80 environment, the Z80 CPU
should be programmed for Mode-2 maskable interrupts.
Table 13. DMA Status
DISABLED
ENABLED
ACTIVE
Inactive (Stopped) Suspended Operating
Description
DMA cannot request the bus (cannot pull DMA can request the bus DMA is bus DMA is bus master
its BUSREQ input to CPU low).
and may have had the bus master but no and is transferring and/
immediately prior to this operations are or searching in one of
state, but it is not
taking place. three modes: Byte,
currently the bus master.
Burst, or Continuous
Can the CPU Yes
write DMA
control bytes
or read DMA
status bytes?
Yes, but first write a No
No
DISABLE DMA
command
External
actions that
cause the
state
Power-down
End-of-block in any RDY line
mode, except with Auto inactive in
Restart. Byte Match in Continuous
any mode. Byte or Burst mode.
mode BAI line inactive.
Loss of power.
RDY line active in
Burst mode, if DMA is
enabled. RETI
instruction fetched by
CPU, if DMA is
enabled and RDY line
is active.
DMA
Any command except the ENABLE DMA ENABLE DMA if RDY ENABLE ENABLE DMA, if
commands command. (And the REINITIALIZE line is inactive and the DMA, if RDY RDY is active or the
(WR6 control STATUS BYTE command, if it is not FORCE READY
line is inactive FORCE is used and
bytes)
preceded by another command.) The command is not used. in Continuous the command is
causing the DISABLE DMA command is specifically
mode.
outside an interrupt
state
designed for this situation.
service routine.
UM008101-0601
Direct Memory Access