Z80 Datasheet, PDF (284/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Table 9. SDLC Transmit Mode (Continued)
Function
Typical Program Steps
Comments
Data Transfer and When Interrupt (Wait Ready) Flags are transmitted by the SIO as soon as
Status
occurs, the CPU performs the Transmit Enable is set and CTS becomes active.
Monitoring
following:
The CTS status change is the first interrupt that
• Changes Transmit Word
Length (if necessary)
• Transfers Data Byte from
CPU (memory) to SIO
• Resets Tx Underrun/EOM
Latch WR0
occurs and is followed by transmit buffer empty
for subsequent transfers. Word length can be
changed on-the-fly for variable I-Field length.
The data byte can contain address, control, or I-
Field information, but not a flag. Reset Tx
Underrun/EOM Latch in the beginning of the
message to avoid a false end-of-frame detection
If the last character of the I- at the receiving end. This ensures that, when
Field is sent, the SIO performs underrun occurs, CRC is transmitted and
the following:
Underrun Interrupt (Tx Underrun/EOM Latch
• Sends CRC
• Sends Closing Flag
• Interrupts CPU with Buffer
active) occurs. Send Abort can be issued to the
SIO in response to any interrupting, continuing
to abort the transmission.
Empty status
The CPU performs the
following:
• Issues Reset Tx Interrupt
Pending Command to the Z80
SIO
• Updates NS count
• Repeats the process for next
message, and more.
If the Vector Indicates an error,
the CPU performs the
following:
• Sends Abort
• Executes Error Routine
• Updates Parameters, Modes,
and more
UM008101-0601
Serial Input/Output