Z80 Datasheet, PDF (92/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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WRQ
7
Base Register Byte
Data
0 BUS
15
87
0
Port A Starting Address Register
Port A Address Counter (see right illustration)
WR1
Block Length Register
Byte Counter (see right illustration)
Base Register Byte
WR2
Port A Variable Timing
Base Register Byte
Port B Variable Timing
WR3
Base Register Byte
Mask Byte
Match Byte
WR4
Base Register Byte
15
87
0
Port B Starting Address Register
Port B Address Counter (see right illustration)
Interrupt Control Byte
Pulse Control Byte
WR5
WR6
Interrupt Vector
Base Register Byte
Base Register Byte
Read Mask
Status Byte (see right)
Data
0 BUS
Port A Address Counter
RR4
Byte Counter
RR2
RR3
RR1
Port B Address Counter
RR6
RR5
Status Byte
RR0
Figure 30. Write Register Organization (left) and Read Register Organization (right)
UM008101-0601
Direct Memory Access