Z80 Datasheet, PDF (190/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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D7 D6 D5 D4 D3 D2 D1 D0
0
0 0 0 Base Register Byte
0 = Port B is Memory
1 = Port B is I/O
0 0 = Port B Address Decrements
0 1 = Port B Address Increments
1
1
0
1
= Port B Address Fixed
Port B Variable
Timing Byte
WR Ends 1/2 Cycle Early = 0
RD Ends 1/2 Cycle Early = 0
0 0 = Cycle Length = 4
0 1 = Cycle Length = 3
1 0 = Cycle Length = 2
1 1 = Do Not Use
MREQ Ends 1/2 Cycle Early = 0 0 = IORQ Ends 1/2 Cycle Early
Figure 78. Write Register 2 Group
D7 D6 D5 D4 D3 D2 D1 D0
0
0 0 Base Register Byte
DMA Enable = 1
Interrupt Enable = 1
1 = Stop on Match
Mask Byte (0 = Compare)
Match Byte
Figure 79. Write Register 3 Group
UM008101-0601
Direct Memory Access