Z80 Datasheet, PDF (283/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
263
Table 9. SDLC Transmit Mode (Continued)
Function
WR4
WR0
WR1
WR0
WR5
WR0
Idle Mode
Typical Program Steps
Comments
Parity Information, SDLC
Mode, X1 Clock Mode
Pointer 1. Reset External/Status
Interrupts
External Interrupt Enable,
The External Interrupt Mode monitors the
Status Affects Vector, Transmit status of the CTS and DCD inputs, as well as
Interrupt Enable or Wait/Ready the status of Tx Underrun/EOM Latch.
Mode Enable
Transmit Interrupt interrupts when the transmit
butter becomes empty; the Wait/Ready mode
can be used to transfer data on a DMA or block
transfer basis. The first Interrupt occurs when
CTS becomes active, at which time flags are
transmitted by the Z80 SIO. The first data byte
(address field) can be loaded in the Z80 SIO
after this interrupt. Flags cannot be sent to the
Z80 SIO as data. Status Affects Vector used in
Channel B only.
Pointer 5
Transmit CRC Enable, Request SDLC-CRC Mode must be defined before
to Send, SDLC-CRC Transmit initializing Transmit CRC Generator
Enable, Transmit Word Length,
Data Terminal Ready
Reset Transmit CRC Generator Initialize CRC Generator to all 1s
Execute Halt Instruction or
some other program
Waiting for Interrupt or Wait/Ready output to
transfer data
UM008101-0601
Serial Input/Output