Z80 Datasheet, PDF (91/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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which control bytes can be written to the DMA while the CPU has the bus
between byte transfers. This allows the next block, which can be an Auto
Restart block, to begin quickly at a new location. Notice that the block
length counter stops (or Auto Restarts) as a result of a comparison to the
block length register. In changing the register, the block length also changes
with what may be unpredictable results.
The pulse-control byte illustrated in Figure 30 (in the WR4 group) also has
a relationship to the byte counter in WR0. The pulse-control byte can be
loaded with an offset value between 0 and 255 and this value is continu-
ously compared with the lower byte of the byte counter. The NT line
generates a pulse each time a match occurs, which happens on every 256
bytes of transfer or search after the initial offset. Because the pulse signals
generated on the NT line only occur when the DMA has control of the
system bus, for example, when the BUSREQ and BUSACK lines are
simultaneously active, the CPU cannot detect theme and they can be
directed exclusively to an external gate, counter, or other device.
Figure 30 illustrates the seven status registers readable through the data bus.
Unlike the write registers, the status registers include no second-level
registers or groups. These registers are accessed sequentially according to
the read mask written to the WR6 group, except that the status byte can be
read separately from the other read registers.
UM008101-0601
Direct Memory Access