Z80 Datasheet, PDF (31/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Table 4. Channel Select Truth Table
CS1
CS0
Channel 0
0
0
Channel l
0
1
Channel 2
1
0
Channel 3
1
1
CE
Chip Enable (input, active Low). A Low level on this pin enables the
CTC to accept control words, interrupt vectors, or time constant data
words from the Z80 data bus during an I/O Write cycle; or to transmit the
contents or the down-counter to the CPU during an I/O Read cycle. In
most applications this signal is decoded from the eight least-significant
bits of the address bus for any of the four I/O port addresses that are
mapped to the four Counter/Timer channels.
Clock(Φ)
System Clock (input). This single-phase clock is used by the CTC to
internally synchronize certain signals.
M1
Machine Cycle One Signal from CPU (input, active low). When M1 is
active and the RD signal is active, the CPU fetches an instruction from
memory. When M1 is active and the IORQ signal is active, the CPU
acknowledges an interrupt, alerting the CTC to place an interrupt vector on
the Z80 data bus if it has daisy-chain priority and one of its channels has
requested an interrupt.
UM008101-0601
Counter/Timer Channels