Z80 Datasheet, PDF (299/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
279
D7 D6 D5 D4 D3 D2 D1 D0
EXE INT Enable
Tx INT Enable
Status Affects Vector
(CH.B Only)
0
0 Rx INT Disable
0
1 Rx INT on First Character
1
0 INT on All Rx Characters (Parity Affects Vector)
*
1
1 INT on All Rx Characters (Parity Does Not Affect Vector)
Wait/Ready on R/T
Wait/Ready Function
Wait/Ready Enable
Figure 115. Write Register 1
*Or on special condition
Table 17. Receive Interrupt Modes
D4
D3
Receive
Receive
Interrupt Mode Interrupt Mode
1
0
Result
0
0
Receive Interrupts Disabled
0
1
Receive Interrupt On First Character Only
1
0
Interrupt On All Receive Characters −
parity error is a Special Receive condition
1
1
Interrupt On All Receive Characters −
parity error is not a Special Receive
condition
Wait/Ready Function Selection (D7-D5). The Wait and Ready functions are
selected by controlling D5, D6, and D7. Wait/Ready function is enabled by
setting Wait/Ready Enable (WR1, D7) to 1. The Ready function is selected
by setting D5 (Wait/Ready function) to 1. If this bit is 1, the WAIT/READY
output switches from High to Low when the Z80 SIO is ready to transfer
UM008101-0601
Serial Input/Output