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| Z80 Datasheet, PDF (48/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS | |||
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< %27 2GTKRJGTCNU
7UGT /CPWCN
CLK
M1
T1
T2
T3
T4
T1
T2
T3
T4
T1
RD
D7âD0
ED
4D
IEI
IEO
INT
*INT goes Low if more interrupts are pending on the RTC.
Figure 13. Return from Interrupt Cycle
Daisy-Chain Interrupt Servicing
Figure 14 illustrates a typical nested interrupt sequence that may occur in
the CTC. In this example, Channel 2 interrupts and is granted service.
While this channel is being serviced, higher priority Channel 1 interrupts
and is granted service. The service routine for the higher priority channel is
completed, and a RETI instruction is executed to signal the channel that its
routine is complete (see âReturn from Interrupt Cycleâ on page 29 for
further details). At this time, the service routine of the lower priority
Channel 2 is resumed and completed.
UM008101-0601
Counter/Timer Channels
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