Z80 Datasheet, PDF (319/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
299
D7 D6 D5 D4 D3 D2 D1 D0
All Sent
I Field Bits
in Previous
Byte
I Field Bits in
Second Previous
Byte
1
0
0
0
3
0
1
0
0
4
1
1
0
0
5
0
0
1
0
6
*
1
0
1
0
7
0
1
1
0
8
1
1
1
1
8
0
0
0
2
8
Parity Error
Rx Overrun Error
CRC/Framing Error
End-of-Frame (SDLC)
*Residue Data for Eight Rx
Bits/Character Programmed
Figure 123. Read Register 1
Parity Error (D4)
When parity is enabled, this bit is set for those characters whose parity does
not match the programmed sense (even/odd). The bit is latched, so when an
error occurs, the bit remains set until given the Error Reset command (WR0).
Receive Overrun Error (D5)
This bit indicates that more than three characters have been received
without a read from the CPU. Only the character that has been written over
is flagged with this error, but when this character is read, the error condition
is latched until reset by the Error Reset command. If Status Affects Vector
is enabled, the character that has been overrun interrupts with a Special
Receive Condition vector.
UM008101-0601
Serial Input/Output