Z80 Datasheet, PDF (210/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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data is available. This signal remains High until a strobe is received from
the peripheral. The rising edge of the strobe generates an interrupt (if it
has been enabled) and causes the Ready line to go inactive. This hand-
shake is similar to those used by many peripheral devices.
By selecting Mode 1, the port enters input mode. To initiate a handshake,
the CPU performs an input read from the port. This activates the Ready
line, which signals the peripheral that data can be loaded to the empty input
register. The peripheral device then strobes data to the port input register
through the strobe line. Again, the rising edge of the strobe causes an inter-
rupt request (if it has been enabled) and deactivates the Ready signal. Data
may be strobed to the input register regardless of the state of the Ready
signal if care is taken to prevent a data overrun condition.
Mode 2 is a bidirectional data transfer mode, utilizing all four handshake
lines. Therefore, only Port A is used for Mode 2 operation. Mode 2 opera-
tion uses the Port A handshake signals for output control, and uses the Port
B handshake signals for input control. Thus, both ARDY and BRDY may
be active simultaneously. The only operational difference between Mode 0
and the output portion of Mode 2 is: Data from the Port A output register is
allowed on the port data bus when ASTB is active. Bidirectional capability
is achieved only when ASTB is active.
Mode 3 operation is used for status and control applications and does not
utilize the handshake signals. When Mode 3 is selected, the next control
word sent to the PIO must define which port data bus lines are inputs and
which are outputs. The format of the control word is depicted below:
D7 D6 D5 D4 D3 D2 D1 D0
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
If any bit is set to a one, then the corresponding data bus line is used as an
input. Conversely, if the bit is reset, the line is used as an output.
During Mode 3 operation, the strobe signal is ignored and the Ready line is
held Low. Data may be written to a port or read from a port by the Z80 CPU
at any time during Mode 3 operation. The data returned from a port to the
UM008101-0601
Parallel Input/Output