Z80 Datasheet, PDF (273/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
253
Table 7. Bisync Receive Mode (Continued)
Function
WR0
WR1
WR0
WR3
Idle Mode
Typical Program Steps
Comments
Pointer 1, Reset External/Status
Interrupt
Status Affects Vector, External
In this interrupt mode, only the first
Interrupt Enable, Receive Interrupt on non-sync data character is transferred to
first character only
the CPU. All subsequent data is
transferred on a DMA basis; however,
special receive condition interrupts
interrupt the CPU. status affects vector
used in Channel B only.
Pointer 3, Enable Interrupt on next
Receive character
Resetting this Interrupt Mode provides
simple program loopback entry for the
next transaction.
Receive Enable, sync character load WR3 is reissued to enable receiver;
inhibit, enter Hunt Mode Auto Enable, receive CRC enable must be set after
receive word length
receiving SOH or STX character.
Execute Halt Instruction or some other Receive mode is fully initialized and the
program
system is waiting for interrupt on first
character.
UM008101-0601
Serial Input/Output