Z80 Datasheet, PDF (198/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Mode Control Reg
(2 Bits)
Internal Bus
Input/Output Select Reg
(8 Bits)
Output Enable
Data Output Reg
(8 Bits)
Mask
Control
Reg
(2 Bits)
8-Bit Peripheral Data
or Control Bus
Mask
Reg
(8 Bits)
Input Data
Interrupt
Requests
Data Input
(8 Bits)
Ready
Handshake Control Logic
(2 Bits)
Strobe
Handshake
Lines
Figure 2. Port I/O Block Diagram
Use the 8-bit mask register and the 8-bit input/output select register only
in the Bit Control mode. In this mode, any of the eight peripheral data or
control bus pins can be programmed to be an input or an output as speci-
fied by the select register. The mask register is used in this mode in
conjunction with a special interrupt feature. This feature allows an inter-
rupt to be generated when any or all of the unmasked pins reach a speci-
fied state (either High or Low).
The 2-bit mask control register specifies the active state desired (High or
Low) and if the interrupt should be generated when all unmasked pins are
active (AND condition) or when any unmasked pin is active (OR condi-
tion). This feature reduces the requirement for CPU status checking of the
peripheral by allowing an interrupt to be automatically generated on
specific peripheral status conditions. For example, in a system with three
alarm conditions, an interrupt may be generated if any one occurs or if all
three occur.
UM008101-0601
Parallel Input/Output