Z80 Datasheet, PDF (211/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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CPU is composed of input data, which comes from port data bus lines
assigned as inputs, and port output register data, which comes from lines
assigned as outputs.
Setting The Interrupt Control Word
The interrupt control word for each port has the following format:
D7 D6 D5 D4 D3 D2 D1 D0
Enable AND/
Int.
OR
High Masks
Low Follows
0
1
11
Used in
Mode 3 Only
Signifies Interrupt
Control Word
If bit D7 = 1, the interrupt enable flip-flop of the port is set and the port
may generate an interrupt. If bit D7 = 0, the enable flag is reset and inter-
rupts may not be generated. If an interrupt is pending when the enable
flag is set, the interrupt is then enabled to the CPU interrupt request line.
Bits D6, D5, and D4 are used only with Mode 3 operation. However,
setting bit D4 of the interrupt control word in any mode of operation
causes a pending interrupt to be reset. These three bits allow interrupts in
Mode 3, but only when specific I/O lines go to defined states. Bit D6
(AND/OR) defines the logical operation to be performed in port moni-
toring. If bit D6 = 1, an AND function is specified and if D6 = 0, an OR
function is specified. For example, if the AND function is specified, all
bits must go to a specified state before an interrupt is generated.
Conversely, the OR function generates an interrupt if any specified bit
goes to the active state.
Bit D5 defines the active polarity of the port data bus line to be monitored.
If bit D5 = 1, the port data lines are monitored for a high state. When bit D5
= 0, the port data lines are monitored for a low state.
If bit D4 = 1, the next control word sent to the PIO must define a mask as
follows:
D7 D6 D5 D4 D3 D2 D1 D0
MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0
UM008101-0601
Parallel Input/Output