Z80 Datasheet, PDF (262/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Table 6. Bisync Transmit Mode
Function
Typical Program Steps
Comments
Register Information loaded
Initialize WR0 Channel Reset, Reset Transmit CRC
Generator
Reset SIO, Initialize CRC Generator
WR0 Pointer 2
WR2 Interrupt Vector
Channel B only
WR0 Pointer 3
WR3 Auto Enables
WR0 Pointer 4
Transmission begins only after CTS
is detected
WR4 Parity Information, Sync Modes
Information, X1Clock Mode
Issue transmit parameters
WR0 Pointer 6
WR6 Sync Character 1
WR0 Pointer 7, Reset External/Status Interrupts
WR7 Sync Character 2
WR0 Pointer 1, Reset External/Status Interrupts
WR1
Status Affects Vector, External Interrupt
Enable, Transmit Interrupt Enable or
WAIT/READY Mode Enable
External Interrupt Mode monitors
the status of CTS and DCD input
pins as well as the status of Tx
Underrun/EOM Latch. Transmit
Interrupt Enable interrupts when the
transmit buffer becomes empty; the
WAIT/READY Mode can be used to
transfer data using DMA or CPU
block transfer.
UM008101-0601
Serial Input/Output