Z80 Datasheet, PDF (263/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
243
Table 6. Bisync Transmit Mode (Continued)
Function
Typical Program Steps
Comments
WR0
WR5
Pointer 5
Status affects vector (Channel B
Request To Send, Transmit Enable, Bisync ^{only). Transmit CRC Enable should}
CRC, transmit character length first Sync ^{be set when first non-sync data is}
Byte To SIO
sent to Z80 SIO. Need several sync
characters in the beginning of
message. Transmitter is fully
initialized.
Idle Mode
Execute Halt Instruction or some other Waiting for interrupt or WAIT/
program
READY output to transfer data.
Data Transfer and When Interrupt (WAIT/READY) occurs: Interrupt Occurs (Wait/ready
Status Monitoring _{• Include/Exclude data byte from CRC}
Accumulation (in SIO)
• Transfer data byte from CPU (or
memory) to SIO
• Detect and set appropriate flags for
control characters (in CPU)
Becomes Active) When first data
byte is being sent, Wait Mode allows
CPU block transfer from memory to
SIO; Ready Mode allows DMA
block transfer from memory to SIO.
The DMA chip can be programmed
to capture special control characters
• Reset Tx Underrun/EOM Latch WR0 if (by examining only the bits that
last character of message is detected
specify ASCII or EBCDIC control
characters), and interrupt CPU.
• Update pointers and parameters (CPU)
Return from Interrupt
Termination
If Error Condition Or Status Change
Occurs:
• Transfer RR0 to CPU
• Execute Error Routine
Tx Underrun/EOM indicates either
Transmit Underrun (sync character
being sent) or end of message (CRC-
16 being sent).
• Return From Interrupt
Redefine Interrupt Modes, Update Modem Program should gracefully terminate
Control outputs (for example, turn off message
RTS)
Disable Transmit Mode
UM008101-0601
Serial Input/Output