Z80 Datasheet, PDF (187/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Interrupt on RDY (interrupt before requesting the bus) does not directly
affect the BUSREQ line. Instead, the interrupt service routine may handle
this by issuing the following commands to WR6:
• Enable after Return From Interrupt (RETI) Command — B7H
• An RETI instruction that resets the Interrupt Under Service (IUS)
latch in the Z80 DMA — EDH, 4DH.
Pulse Generation
When the pulse generation option is selected, the INT line is driven Low
every 256 bytes after the offset value. The line goes Low during the DMA
cycle in which the pulse-control byte matches the lower byte of the byte
counter, and it remains Low for one complete transfer cycle. A transfer
cycle is defined as either a read cycle (search-only or simultaneous transfer
operations) or a read plus a write cycle, where read and write cycles can be
independently programmed for length through the variable-cycle option.
UM008101-0601
Direct Memory Access