Z80 Datasheet, PDF (138/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Table 15. Control Byte Order (Continued)
Maximum Number of Z80 CPU
Initialization/Reinitialization Sequence Bytes
REINITIALIZE STATUS BYTE
1
Command
READ MASK FOLLOWS Command 1
Read Mask Control Byte
1
INITIATE READ SEQUENCE
1
Command
FORCE READY Command
1
ENABLE INTERRUPTS Command 1
ENABLE DMA Command
1
Total
35
Port Designation
Either Port A or Port B can be selected as the source or destination, (illus-
trated in Figure 19) because both ports feature the same degree of program-
mability. When the destination port is also a fixed-address port, see the
section “Fixed-Address Destination Ports.” Port characteristics are spec-
ified in the following control byte groups:
Port A
WR0
WR1
WR6
Port B
WR0
WR2
WR4
WR6
In a transfer, if the direction of transfer (bit 2 of WR0) changes, the WR0
control byte must be preceded by a different control byte, thereby insuring
that the DMA is disabled.
UM008101-0601
Direct Memory Access