Z80 Datasheet, PDF (137/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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interrupts and reinitialization of the status byte as well as many other func-
tions, including class and mode designation, port designation, address and
block-length designation.
Table 15 lists the order in which control bytes must be written for the
initialization or reinitialization because of program abort. Some of these
control bytes may not be relevant to a specific application. All commands
referred to are WR6 control bytes. Thirty-five control bytes occur when all
of the control bytes are written.
All control bytes written to the DMA disable the DMA, except the
ENABLE DMA command and possibly also the REINITIALIZE STATUS
BYTE command and the WR0 control byte (when changing transfer direc-
tions). The ENABLE DMA command must always be the last command
written after any communication between the CPU and DMA if the DMA
is to continue operating. Furthermore, communication with the DMA can
only occur when the CPU is bus master.
Table 15. Control Byte Order
Maximum Number of Z80 CPU
Initialization/Reinitialization Sequence Bytes
DISABLE DMA Command
1
RESET Command (Multiple)
6
WR0 Control Bytes
5
WR1 Control Bytes
2
WR2 Control Bytes
2
WR3 Control Bytes
3
WR4 Control Bytes
5
WR5 Control Bytes
1
RESET PORT A TIMING Command 1
RESET PORT B TIMING Command 1
LOAD Command
1
UM008101-0601
Direct Memory Access