Z80 Datasheet, PDF (192/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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D7 D6 D5 D4 D3 D2 D1 D0
10
0 1 0 Base Register Byte
0 = Ready Active Low
1 = Ready Active High
0 = CE Only
1 = CE/WAIT Multiplexed
0 = Stop on End-of-Block
1 = Auto Restart on End-of-Block
Figure 81. Write Register 5 Group
D7 D6 D5 D4 D3 D2 D1 D0
1
1 1 Base Register Byte
Hex Command Name
1 0 0 0 0 = C3 = Reset
1 0 0 0 1 = C7 = Reset Port A Timing
1 0 0 1 0 = C8 = Reset Port B Timing
1 0 0 1 1 = CF = Load
1 0 1 0 0 = D3 = Continue
0 1 0 1 1 = AF = Disable Interrupts
0 1 0 1 0 = AB = Enable Interrupts
0 1 0 0 0 = A3 = Reset and Disable Interrupts
0 1 1 0 1 = B7 = Enable after RETI
0 1 1 1 1 = BF = Read Status Byte
0 0 0 1 0 = 8B = Reinitialize Status Byte
0 1 0 0 1 = A7 = Initialize Read Sequence
0 1 1 0 0 = B3 = Force Ready
0 0 0 0 1 = 87 = Enable DMA
0 0 0 0 0 = 83 = Disable DMA
0 1 1 1 0 = BB = Read Mask Follows
0
Base Register Byte
Status Byte
Byte Counter (Low Byte)
Byte Counter (High Byte)
Port A Address (Low Byte)
Port A Address (High Byte)
Port B Address (Low Byte)
Port B Address (High Byte)
Figure 82. Write Register 6 Group
UM008101-0601
Direct Memory Access