Z80 Datasheet, PDF (102/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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MEMORY
A.
Jump Table
CPU
I Register
DMA
Interrupt
Vector
B.
Jump Table
Service Routine
Program
Counter
C.
Service Routine
Register
Program
Counter
Figure 33. Interrupt Service Routine
Write
Registers
Interrupt Latches
Two primary latches are associated with the interrupt structure:
• Interrupt Pending (IP). Set whenever the DMA requests an interrupt
but has not yet acknowledged. It holds the INT line Low (Figure 34).
• Interrupt Under Service (IUS). Set when the CPU acknowledges the
DMA interrupt (Figure 35). This accomplishes three things:
– Prevents further interrupts by this DMA
UM008101-0601
Direct Memory Access