Z80 Datasheet, PDF (254/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Table 4. Asynchronous Mode (Continued)
Function
Typical Program Steps
Comments
WR5
WR0
WR1
Idle Mode
Data transfer and
error monitoring
Request to send, transmit enable, transmit
character length, data terminal ready
Receive and Transmit both
fully initialized. Auto Enables
enables transmitter if CTS is
active and receiver if DCD is
active
Pointer 1, Reset External/Status Interrupt
Transmit Interrupt Enable, Status Affects
Transmit/receive Interrupt
Vector,
Mode Selected.
Interrupt on all Receive characters. Disable External Interrupt monitors the
Wait/Ready function, External Interrupt Enable status of the CTS, DCD, and
SYNC inputs and detects the
Break sequence. Status affects
Vector In Channel B only. This
data byte must be transferred or
no transmit interrupts occur.
Transfer first data byte to SIO
Execute Halt Instruction or other program
Program is waiting for an
interrupt from the SIO
Z80 Interrupt Acknowledge cycle transfers
RR2 to CPU
If a character is received:
• Transfer data character to CPU
When the interrupt occurs, the
interrupt vector is modified by:
1) Receive character available;
2) Transmit buffer empty;
3) External/status change; and
4) Special receive condition.
• Update pointers and parameters
• Return from Interrupt
If transmitter buffer is empty:
• Transfer data character to SIO
• Update pointers and parameters
• Return from interrupt
Program control is transferred
to one of the eight Interrupt
Service routines.
UM008101-0601
Serial Input/Output