Z80 Datasheet, PDF (47/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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CLK
M1
IORQ
RD
IEI
T₁
T₂
T_W*
T_W*
T₃
T₄
T₁
INT
DATA
Vector
Figure 12. Interrupt Acknowledge Cycle
Return from Interrupt Cycle
Figure 13 illustrates the timing associated with the RETI Instruction. This
instruction is used at the end of an Interrupt Service Routine to initialize
the daisy-chain enable lines for control of nested priority interrupt
handling. The CTC decodes the two-byte RETI code internally and
determines whether it is intended for a channel being serviced.
When several Z80 peripheral chips are in the daisy-chain, IEI becomes
active on the chip currently under service when an EDH Op Code is
decoded. If the following Op Code is 4DH, the peripheral being serviced is
re-initialized and its IEO becomes active.
UM008101-0601
Counter/Timer Channels