Z80 Datasheet, PDF (57/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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also requires external logic and inhibits memory refresh. Additionally, it
reduces DMA throughput.
All DMA transfers interrupt dynamic memory refresh by the CPU and
most of them idle the CPU. It is, therefore, important to consider these
implications when making the trade-off for higher DMA transfer speed.
A.
Conventional
Programmed
Instruction
Sequence
Fetch and Read Cycles
Write Cycle
CPU
MEMORY
I/O
BUS
DMA
B.
Z80/Z8000
Block Transfer
Instruction
Write Cycle
Read Cycle
CPU
MEMORY
I/O
BUS
DMA
C.
DMA
Sequential
Instruction
CPU
Read Cycle
Write Cycle
BUS
MEMORY
I/O
DMA
D.
DMA
Simultaneous
Transfers
CPU
Read/Write Cycle
BUS
MEMORY
I/O
DMA
Figure 16. Conceptual Comparison of Various I/O Transfer Methods
UM008101-0601
Direct Memory Access