Z80 Datasheet, PDF (150/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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A DMA responds to
I/O addresses 00H
through 77H
Z80
CPU
M1
IORQ
Address Bus
A7
M1 IORQ
CE
DMA
CPU
A7
A0
B PROM determines
DMA response
M1
IORQ
A7
04
CE3
256X4 03
CE2
PROM 02
A0
01
CE1
M1 IORQ
CE
DMA
CPU
C DMA responds to
I/O addresses E0H
through E3H
M1
IORQ
A0 ^A7
A5
M1 IORQ
DMA
A3 ^A4
A2
E ^{S0 S1 S2}
E ^74LS138
E _01234567
....
CE
CE7
CE1
Figure 49. Chip Enable Decoding with Z80 CPU
Use of WAIT Input
When the DMA is bus master, the CE/WAIT pin functions as an input from
memory or I/O logic that may extend read or write cycles by requesting
Waits states. An active BUSACK output from the CPU signals that the
UM008101-0601
Direct Memory Access