Z80 Datasheet, PDF (253/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
233
Table 3. Contents of Write Registers 3, 4, and 5 in Asynchronous Modes (Continued)
Bit 7
WR5 DTR
Bit 6
Bit 5
Bit 4 Bit 3
00 = Tx 5 Bits (or less)/
Char
Send Tx
10 = Tx 6 Bits/Char Break Enable
01 = Tx 7 Bits/Char
11 = Tx 8 Bits/Char
Bit 2 Bit 1
0
RTS
Bit 0
0
Table 4. Asynchronous Mode
Function
Typical Program Steps
Comments
Register: Information loaded:
Initialize WR0 Channel Reset
Reset SIO
WR0 Pointer 2
WR2 Interrupt Vector
Channel B Only
WR0 Pointer 4, Reset External/Status Interrupt
WR4 Asynchronous mode, Parity information, Stop Issue Parameters
Bits information, Clock Rate information
WR0 Pointer 3
WR3 Receive Enable, Auto Enables, Receive
Character Length
WR0 Pointer 5
UM008101-0601
Serial Input/Output