Z80 Datasheet, PDF (307/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
287
used for both the receiver and transmitter. The system clock in all modes
must be set to at least 4.5 times the data rate. If the x1 clock rate is selected,
bit synchronization must be performed externally.
Table 25. Clock Rate
Clock Rate 1
0
0
1
1
Clock Rate 0 Result
0
Data Rate x1 = Clock Rate
1
Data Rate x16 = Clock Rate
0
Data Rate x32 = Clock Rate
1
Data Rate x64 = Clock Rate
Write Register 5
WR5 contains control bits that affect the operation of transmitter, with the
exception of D2, which affects the transmitter and receiver.
Table 26. Write Register 5 Transmitter Control
D7
DTR
D6
Tx
Bits/
Char 1
D5
Tx
Bits/
Char 0
D4
Send
Break
D3
Tx
Enable
D2
D1
CRC-16/ RTS
SDLC
DO
Tx
CRC
Enable
Transmit CRC Enable (D0)
This bit determines if CRC is calculated on a specific transmit character. If
it is set at the time the character is loaded from the transmit buffer into the
transmit shift register, CRC is calculated on the character. CRC is not auto-
matically sent unless this bit is set when the Transmit Underrun condition
occurs.
UM008101-0601
Serial Input/Output