Z80 Datasheet, PDF (44/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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CLK
CS0. CS1, CE
IORQ
T₁
T₂
T_WA
T₃
T₁
Channel Address
RD
M1
DATA
OUT
Figure 10. CTC Read Cycle
CTC Counting and Timing
Figure 11 illustrates the timing diagram for the CTC Counting and Timing
modes.
In the Counter mode, the edge (rising edge is active in this example) from
the external hardware connected to pin CLK/TRG, decrements the down-
counter in synchronization with the System Clock Φ. This CLK/TRG pulse
must have a minimum width and the minimum period must not be less than
twice the System clock period. Although there is no setup time requirement
between the active edge of the CLK/TRG and the rising edge of Φ, if the
CLK/TRG edge occurs closer than a specified minimum time, the
decrement of the down-counter will be delayed one cycle of Φ.
Immediately after the 1 to 0 decrement of the down-counter, the ZC/TO
output is pulsed true.
In the Timer mode, a pulse trigger (user selectable as either active High or
active Low) at the CLK/TRG pin enables the timing function on the second
succeeding rising edge of Φ. As in the Counter mode, the triggering pulse is
UM008101-0601
Counter/Timer Channels