Z80 Datasheet, PDF (146/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Table 16. Sample DMA Program (Continued)
D7
WR4 sets mode to 1 1
Burst and sets DMA
to expect Port B
address
Port B address
(lower)
WR5 sets Ready
active High
00
10
WR6 loads Port B 1 1
address and resets
block counter *
WR0 sets Port A as 0 0
source *
WR6 loads Port A 1 1
address
and resets block
counter
WR6 enables DMA 1 0
to start operation.
D5
D4
D3
D2 D1
0
0
0
1
0
No No Port B
Interrup Upper Lower
t Address Address
Control
Follows
Byte
Follows
0
0
0
1
0
D0 HEX
1 C5
1
05
0
0
1
0
No No Wait RDY
Auto Status Active
Restart
High
0
0
1
1
1
0 8A
1
1 CF
0
0
0
No Address or Block
Length Bytes
0
0
1
1
0
1
05
B→A _{Transfer No}
Search
1
1
1 CF
0
0
0
1
1
1
87
UM008101-0601
Direct Memory Access