UPSD33XX Datasheet, PDF (99/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Serial I/O Engine (SIOE)
At the heart of the I²C interface is the hardware
SIOE, shown in Figure 40. The SIOE automatically
handles low-level I²C bus protocol (data shifting,
handshaking, arbitration, clock generation and
synchronization) and it is controlled and monitored
by five SFRs.
The five SFRs shown in Figure 40 are:
■ S1CON - Interface Control (Table
50., page 100)
Figure 40. I²C Interface SIOE Block Diagram
■ S1STA - Interface Status (Table
52., page 103)
■ S1DAT - Data Shift Register (Table
53., page 104)
■ S1ADR - Device Address (Table
54., page 104)
■ S1SETUP - Sampling Rate (Table
55., page 105)
INTR to 8032
SCL / P3.7
8
S1STA - Interface Status
8
S1CON - Interface Control
S1SETUP - Sample Rate
8
Control (START Condition)
Open-
Drain
Output
Input
SDA / P3.6
Arbitration
and Sync
Clock
Generation
Timing and
Control
Periph
Clock
(fOSC)
Open-
Drain
Output
Input
Serial DATA OUT
AI09626
Serial DATA IN
8
Shift Direction
b7
S1DAT - Shift Register
ACK
b0 Bit
7
Comparator
7
b7
b0
8
S1ADR - Device Address
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