UPSD33XX Datasheet, PDF (215/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 140. CPLD Macrocell Synchronous Clock Mode Timing (3V PSD Module)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo ^Slew
Off _rate⁽¹⁾
Unit
Maximum Frequency
External Feedback
1/(t_S+t_CO)
23.2
MHz
f_MAX
Maximum Frequency
Internal Feedback (f_CNT)
1/(t_S+t_CO–10)
30.3
MHz
Maximum Frequency
Pipelined Data
1/(t_CH+t_CL)
40.0
MHz
t_S Input Setup Time
20
+ 4 + 15
ns
t_H Input Hold Time
0
ns
t_CH Clock High Time
Clock Input
15
ns
t_CL Clock Low Time
Clock Input
10
ns
t_CO Clock to Output Delay
Clock Input
23
– 6 ns
t_ARD CPLD Array Delay
Any macrocell
20
+4
ns
t_{MIN Minimum Clock Period}⁽²⁾
t_CH+t_CL
25
ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL.
215/231