UPSD33XX Datasheet, PDF (119/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 62. SPISTAT: SPI Interface Status Register (SFR D3h, Reset Value 02h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
–
BUSY
TEISF
RORISF
TISF
RISF
Details
Bit
Symbol
R/W
Definition
7-5
–
–
Reserved
SPI Busy
4
BUSY
R
0 = Transmit or Receive is completed
1 = Transmit or Receive is in process
Transmission End Interrupt Source flag
3
TEISF
R
0 = Automatically resets to '0' when firmware reads this register
1 = Automatically sets to '1' when transmission end occurs
Receive Overrun Interrupt Source flag
2
RORISF
R
0 = Automatically resets to '0' when firmware reads this register
1 = Automatically sets to '1' when receive overrun occurs
Transfer Interrupt Source flag
1
TISF
R
0 = Automatically resets to '0' when SPITDR is full (just after the SPITDR
is written)
1 = Automatically sets to '1' when SPITDR is empty (just after byte loads
from SPITDR into SPI shift register)
Receive Interrupt Source flag
0
RISF
R
0 = Automatically resets to '0' when SPIRDR is empty (after the SPIRDR
is read)
1 = Automatically sets to '1' when SPIRDR is full
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