UPSD33XX Datasheet, PDF (147/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
PSD Module Detailed Operation
Specific details are given here for the following key
functional areas on the PSD Module:
■ Flash Memories
■ PLDs (DPLD and GPLD)
■ I/O Ports
■ Power Management
■ JTAG ISP and Debug Interface
Flash Memory Operation. The Flash memories
are accessed through the 8032 Address, Data,
and Control Bus interfaces. Flash memories (and
SRAM) cannot be accessed by any other bus
master other than the 8032 MCU (these are not
dual-port memories).
The 8032 cannot write to Flash memory as it
would an SRAM (supply address, supply data,
supply WR strobe, assume the data was correctly
written to memory). Flash memory must first be
“unlocked” with a special instruction sequence of
byte WRITE operations to invoke an internal algo-
rithm inside either Flash memory array, then a sin-
gle data byte is written (programmed) to the Flash
memory array, then programming status is
checked by a byte READ operation or by checking
the Ready/Busy pin (PC3). Table 80., page 148
lists all of the special instruction sequences to pro-
gram a byte to either of the Flash memory arrays,
erase the arrays, and check for different types of
status from the arrays.
This unlocking sequence is typical for many Flash
memories to prevent accidental WRITEs by errant
code. However, it is possible to bypass this un-
locking sequence to save time while intentionally
programming Flash memory.
IMPORTANT: The 8032 may not read and exe-
cute code from the same Flash memory array for
which it is directing an instruction sequence. Or
more simply stated, the 8032 may not read code
from the same Flash array that is writing or eras-
ing. Instead, the 8032 must execute code from an
alternate memory (like SRAM or a different Flash
array) while sending instruction sequences to a
given Flash array. Since the two Flash memory ar-
rays inside the PSD Module device are completely
independent, the 8032 may read code from one
array while sending instructions to the other. It is
possible, however, to suspend a sector erase op-
eration in one particular Flash array in order to ac-
cess a different sector within that same Flash
array, then resume the erase later.
After a Flash memory array is programmed or
erased it will go to “Read Array” mode, then the
8032 can read from Flash memory just as it would
read from any 8-bit ROM or SRAM device.
Flash Memory Instruction Sequences. An in-
struction sequence consists of a sequence of spe-
cific byte WRITE and byte READ operations. Each
byte written to either Flash memory array on the
PSD Module is received by a state machine inside
the Flash array and sequentially decoded to exe-
cute an embedded algorithm. The algorithm is ex-
ecuted when the correct number of bytes are
properly received and the time between two con-
secutive bytes is shorter than the time-out period
of 80µs. Some instruction sequences are struc-
tured to include READ operations after the initial
WRITE operations.
An instruction sequence must be followed exactly.
Any invalid combination of instruction bytes or
time-out between two consecutive bytes while ad-
dressing Flash memory resets the PSD Module
Flash logic into Read Array mode (where Flash
memory is read like a ROM device). The Flash
memories support instruction sequences summa-
rized in Table 80., page 148.
■ Program a Byte
■ Unlock Sequence Bypass
■ Erase memory by array or by sector
■ Suspend or resume a sector erase
■ Reset to Read Array mode
The first two bytes of an instruction sequence are
8032 bus WRITE operations to “unlock” the Flash
array, followed by writing a command byte. The
bus operations consist of writing the data AAh to
address X555h during the first bus cycle and data
55h to address XAAAh during the second bus cy-
cle. 8032 address signals A12-A15 are “Don’t
care” during the instruction sequence during
WRITE cycles. However, the appropriate sector
select signal (FSx or CSBOOTx) from the DPLD
must be active during the entire instruction se-
quence to complete the entire 8032 address (this
includes the page number when memory paging is
used). Ignoring A12-A15 means the user has more
flexibility in memory mapping. For example, in
many traditional Flash memories, instruction se-
quences must be written to addresses AAAAh and
5555h, not XAAAh and X555h like supported on
the PSD Module. When AAAAh and 5555h must
be written to, the memory mapping options are lim-
ited.
The Main Flash and Secondary Flash memories
each have the same instruction set shown in Table
80., page 148, but the sector select signals deter-
mine which memory array will receive and execute
the instructions.
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