UPSD33XX Datasheet, PDF (177/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Latched Address Output Mode. In the MCU
Module, the data bus Bits D0-D15 are multiplexed
with the low address Bits A0-A15, and the ALE sig-
nal is used to separate them with respect to time.
Sometimes it is necessary to send de-multiplexed
address signals to external peripherals or memory
devices. Latched Address Output mode will drive
individual demuxed address signals on pins of
Ports A or B. Port pins can be designated for this
function on a pin-by-pin basis, meaning that an en-
tire port will not be sacrificed if only a few address
signals are needed.
To activate this mode, the desired pins on Port A
or Port B are designated as “Latched Address Out”
in PSDsoft. Then in the 8032 initialization firm-
ware, a logic ’1’ is written to the csiop Control reg-
ister for Port A or Port B in each bit position that
corresponds to the pin of the port driving an ad-
dress signal. Table 107 and Table 108 define the
csiop Control register locations and bit assign-
ments.
The latched low address byte A4-A7 is available
on both Port A and Port B. The high address byte
A8-A15 is available on Port B only. Selection of
high or low address byte is specified in PSDsoft
Express.
Table 107. Latched Address Output, Port A Control Register⁽¹⁾ (address = csiop + offset 02h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA7
(addr A7)
PA6
(addr A6)
PA5
(addr A5)
PA4
(addr A4)
PA3
(addr A3)
PA2
(Addr A2)
PA1
(addr A1)
PA0
(addr A0)
Note: 1. Port A not available on 52-pin uPSD33xx devices
2. For each bit, 1 = drive demuxed 8032 address signal on pin, 0 = pin is default mode, MCU I/O
3. Default state for register is 00h after reset or power-up
Table 108. Latched Address Output, Port B Control Register (address = csiop + offset 03h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PB7
(addr A7 or
A15)
PB6
(addr A6 or
A14)
PB5
(addr A5 or
A13)
PB4
(addr A4 or
A12)
PB3
(addr A3 or
A11)
PB2
(Addr A2 or
A10)
PB1
(addr A1 or
A9)
PB0
(addr A0 or
A8)
Note: 1. For each bit, 1 = drive demuxed 8032 address signal on pin, 0 = pin is default mode, MCU I/O
2. Default state for register is 00h after reset or power-up
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