UPSD33XX Datasheet, PDF (97/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

– An Acknowlegde bit is generated from a
Master or a Slave by driving SDA low during
the “ninth” bit time, just following each 8-bit
byte that is transfered on the bus (Figure
39., page 97). A Non-Acknowledge occurs
when SDA is asserted high during the ninth bit
time. All byte transfers on the I²C bus include
a 9th bit time reserved for an Acknowlege
(ACK) or Non-Acknowledge (NACK).
Figure 39. Data Transfer on an I²C Bus
7-bit Slave
Address
READ/WRITE
Indicator
MSB
R/W ACK
Start
Condition
1
2 3-6
7
8
9
Clock can be held low
to stall transfer.
uPSD33xx
– An additional Master device that desires to
control the bus should wait until the bus is not
busy before generating a START condition so
that a possible Slave operation is not
interrupted.
– If two Master devices both try to generate a
START condition simultaneously, the Master
who looses arbitration will switch immediately
to Slave mode so it can recoginize it’s own
Slave address should it appear on the bus.
Acknowledge
bits from
receiver
MSB
NACK
ACK
1
2
3-8
9
Repeated if more
data bytes are
transferred.
Stop
Condition
Repeated
Start
Condition
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