UPSD33XX Datasheet, PDF (182/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Port B Structure. Port B supports the following
operating modes:
■ MCU I/O Mode
■ GPLD Output Mode from Output Macrocells
MCELLABx, or MCELLBCx (OMC allocator
routes these signals)
■ GPLD Input Mode to Input Macrocells IMCBx
■ Latched Address Output Mode
Port B also supports Open Drain/Slew Rate output
drive type options using the csiop Drive Select reg-
isters. Pins PB0-PB3 can be configured to fast
slew rate, pins PB4-PB7 can be configured to
Open Drain Mode.
See Figure 75 for detail.
Figure 75. Port B Structure
FROM AND-
OR ARRAY
FROM PLD
INPUT BUS
FROM OMC
ALLOCATOR
PT OUTPUT ENABLE (.OE)
PSD MODULE RESET
Q ^DIRECTION
CSIOP
REGIS-
8032 ^TERS
DATA
Q
DRIVE
BITS _D
8032
WR
Q ^CONTROL
(MCUI/O)
Q ^{DATA OUT}
CLR
RESET
LATCHED ADDR BIT
8032
DATA
BIT
1 ^DIRECTION
P ₂ ^{DRIVE SELECT}
D
B
3
CONTROL
DATA OUT
M ₄ ^(MCUI/O)
U ₅ ^{ENABLE OUT}
X ₆ DATA IN (MCUI/O)
8032 RD
ONE of 6
CSIOP
REGISTERS
FROM OMC OUTPUT
(MCELLABx or MCELLBCx)
I/O PORT B
LOGIC
PSDsoft
OUTPUT
SELECT
1^O
U
T
P
U
2T
3_M
U
X
DRIVE TYPE SELECT⁽¹⁾
1 = OPEN
DRAIN,
PB4 - PB7
1 = FAST
SLEW RATE,
PB0 - PB3
V_DD V_DD
OUTPUT
ENABLE
PIN
OUTPUT
OUTPUT
ENABLE
TYPICAL
PIN, PORT B
CMOS
BUFFER _{PIN INPUT}
NO
HYSTERESIS
TO IMCs
IMCB0 - IMCB7
AI09180
Note: 1. Port pins PB0-PB3 are capable of Fast Slew Rate output drive option. Port pins PB4-PB7 are capable of Open Drain output option.
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